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Altera_Forum's avatar
Altera_Forum
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13 years ago

Constrain delay of internal paths

Hi All, Here is my clocking setup. I have the main clock coming into a pin and then into a 1-to-1 PLL. The PLL output is tapped off to local routing. From that routing it comes out in a tree...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I'm using a command line flow, due to tying into other CAD tools, so would it be something like

set_location_assignment -to clk_control|cntrl1|outnode|combout X1_Y1

not really sure what the format after -to should be. I suppose I can use the gui to do a test and see what it creates in the .qsf.

Thanks again