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Altera_Forum
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13 years ago

Constrain delay of internal paths

Hi All, Here is my clocking setup. I have the main clock coming into a pin and then into a 1-to-1 PLL. The PLL output is tapped off to local routing. From that routing it comes out in a tree...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Put the node name in the To column in the assignment editor, choose Location for assignment type, and put in an X/Y co-ordinate, like "X1_Y1". If you want to find the co-ordinates, locate them in the Chip Planner. (Wherever you point, the x/y co-ordinates are shown in the top-left)