Constrain delay of internal paths

Thanks Rysc,

I already have the keep attribute on the ungated clock, so I don't have an uneven number of global clock buffers causing the delay mismatch. Removing the clock gating is not desirable, it's emulating an ASIC so we want to keep alterations to a minimum. I forced all four onto the same quadrant of global buffers, and that helped a lot, before the fitter had the cluster of logic in one spot that was not the chip center, and using global buffers in different quadrants. I might try your altclkctrl suggestion as well, as it might get an even closer match. Unfortunately I think if I need more that these four, I'll need to use another quadrant, which means I'll need to control the LUT location as well and not just depend on the P&R to shove them all close to each other. I'd rather not have to figure out how to manually control placement...