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Yes, I think so. You can examine in netlist viewers, where the multiplier logic is hidden. Part of the logic is probably placed in target register LE. When predicting number of logic terms, did you consider limited number of inputs with existing LEs?
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Yes, you are right, some of LUT are merged into the target Registers (but the sum is still smaller than number of LUTs obtained by synthesizing Multiplier alone. <The logic synthesis ignores obtimization when circuit is too small compared to FPGA size, possible?????> )
I'm trying to predict for Cyclone at the moment. Of course it's great if prediction can be applied for other Family as well.
Thanks a lot
Jeff
Honored Contributor
