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Altera_Forum
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9 years ago

Connecting HPS to FPGA DDR3 takes up all the address space

Hello, Using QSYS, I connected the HPS of a Cyclone V SOC to a DDR3 Controller on the fabric side via the HPS's H2F_AXI_MASTER bus. The DDR3 Controller is assigned address: 0x0000_0000 to 0x3...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

The first row in the table is The H2F_AXI_MASTER bus that you are inquiring about.

The addresses shown are from the ARM perspective.

The addresses within Qsys are from the FPGA perspective.