Connecting data and instruction bus to different ports

Hello,

I am interested in connecting the data and instruction bus from the Nios core to different ports of a bridge.

My first question is whether or not there is documentation anywhere that describes in more detail the range of options for custom tcl descriptions of QSYS modules.

For instance, to make a bridge:

set_interface_property s0 bridgesToMaster m0

I can't find documentation for that anywhere... not even here:http://www.altera.com/literature/hb/qts/qsys_tcl.pdf

Anyhow, I would like to create a bridge where the instruction and data have their own ports, but only one outgoing master to memory.

QSYS gives an error when connecting instruction and data to different ports, even if those ports both have the same address range and bridge to the same master port.

QSYS seems to treat the instruction and data buses as a single bus, so I get the same error as if I connected the data bus alone to two different modules with overlapping addresses.

There has to be some way to do this because this is how the interconnect logic works. But the altera_merlin_interconnect_interconnect_wrapper_hw.tcl file has no useful info in it.

There are these lines from the altera_merlin_master_translator_hw.tcl:

set_interface_assignment avalon_anti_master_0 merlin.flow.avalon_universal_master_0 avalon_universal_master_0
set_interface_assignment avalon_universal_master_0 merlin.flow.avalon_anti_master_0 avalon_anti_master_0

I'm going to try them out and hopefully they work, but can anybody explain what exactly they do anyway?

Or just how to solve this problem of connecting the data and instruction to separate ports of a bridge to main memory?

Thanks,

Jonah