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Altera_Forum
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15 years ago

Confusion about Source-Synchronous constraints

Hi, everyone: I use FPGA to capture the output data of ADC. The ADC output timing is as follows: https://www.alteraforum.com/forum/attachment.php?attachmentid=3894 In Altera's "AN 433 ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I understand this issue better. Thank you very much for your help.