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Altera_Forum
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14 years ago

Confusion about Source-Synchronous constraints

Hi, everyone: I use FPGA to capture the output data of ADC. The ADC output timing is as follows: https://www.alteraforum.com/forum/attachment.php?attachmentid=3894 In Altera's "AN 433 ...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi,

UI is the lazy format for Unit Interval. i.e. clock period(if interface is single data rate) or (half clock period if interface is DDR).

Don't worry about virtual clock or set output issue. Just enter set input delay and that should be enough. If you don't get timing right then you can look for other options.