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Altera_Forum
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9 years ago

Confused with set_input/output_delay command

Hi folks, while I am familiar with set_input/output_delay -max where it specifies the maximum time taken for the data to travel to and from FPGA, I am still very confused with -min value. I noticed i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Now that makes more sense - iExt and oExt are independent on clock edges (Setup/Hold Relationship) but the edges are mainly used for calculating slacks.

What if I have a scenario where I am connecting FPGA-FPGA. How do I calculate the iExt and oExt as Tco, Tsu and Th are not fixed, right?