Confused with set_input/output_delay command

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If the data arrives before the specified clock edge, then the delay is negative. The maximum or minimum delays specified could be positive or negative. The only restriction is that max > min.

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I believe that when we mention data vs clock relationship it will be different between setup and hold, right? i.e-:

1) Setup : data vs clock edge at next clock cycle (setup relationship of clock period)

2) Hold : data vs clock edge at current clock cycle (hold relationship of 0ns)