Altera_Forum
Honored Contributor
11 years agoConduit(s)?
Hi, today I'm asking myself: Why do I need to use different conduits e.g. "conduit_end_0", "conduit_end_1", etc.? Or can I declare all my own signals with the same "conduit_end"? Or isn't there any difference at all?
For example, I have a simple Avalon MM Slave getting data from the HPS. The data is written to the FPGA and read from the FPGA by "writedata" with flag "write" and "readdata" with flag "read". I saw in Qsys, even the Avalon MM Slave template automatically assigns it all the name "conduit_end_0". So, is this correct, or should I create a separate "new Conduit" i.e. "conduit_end_1" for write? What happens if I create separate conduits for each signal? Is there a difference at all?