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RHerm1's avatar
RHerm1
Icon for New Contributor rankNew Contributor
6 years ago

Concatenation operator in a port assignment ?

I'm using Quartus 18.1.1 / Build 646 and have observed a strange behavior with the following VHDL code: meta_data_ram : altsyncram generic map ( ....... ) port map ( address_a => md_...
MEIYAN_L_Intel's avatar
MEIYAN_L_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi,

I had found out that it might be due to the VHDL version used in Quartus.

For an example here:

In VHDL 2008:

comp_inst : comp

port map(

thing => "000" & sig

);

In VHDL 93:

tempsig <= "000" & sig;

comp_inst : comp

port map(

thing => tempsig

);

You may check your VHDL version in by clicking assignment >settings>VHDL input.

Thanks