Forum Discussion
RHerm1
New Contributor
New ContributorConcatenation operator in a port assignment ?
I'm using Quartus 18.1.1 / Build 646 and have observed a strange behavior with the following VHDL code: meta_data_ram : altsyncram
generic map (
.......
)
port map (
address_a => md_...
MEIYAN_L_Intel
Frequent Contributor
Frequent ContributorHi,
I had found out that it might be due to the VHDL version used in Quartus.
For an example here:
In VHDL 2008:
comp_inst : comp
port map(
thing => "000" & sig
);
In VHDL 93:
tempsig <= "000" & sig;
comp_inst : comp
port map(
thing => tempsig
);
You may check your VHDL version in by clicking assignment >settings>VHDL input.
Thanks
