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Altera_Forum
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18 years ago

Component Editor calculates wrong address size from verilog file

I have components from 6.x that were working correctly but when upgraded to new 7.2 component do not. Snippet: I define `define uart_addr_width 3 and use to set the address width in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

I hit a similar problem using Verilog parameters to create SOPC custom components. At the end I changed everything to plain old integers and filed a service request. It's currently flagged for a fix in Quartus 8.0.