Component Editor calculates wrong address size from verilog file

FvM - I see the problem in the component editor after I load the HDL file. The tab that lists the signals has the incorrect signal width. I have not added this new component to an SOPC design yet. I listed the addr bus in the example, but the data bus is also effected and generates a component editor warning that the data bus is not 8,16,32 bits wide. I don't think the value is being overwritten as I only define/use it in the top level file and the reported value is always 1 more than the value I put in the define.

avemo- I had seen some previous posts about VHDL defines/generics having to be all capital letters to be able to work. I'm not sure if that will solve your problem, but all caps didn't make any difference with verilog.