Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Component Editor calculates wrong address size from verilog file

I have components from 6.x that were working correctly but when upgraded to new 7.2 component do not. Snippet: I define `define uart_addr_width 3 and use to set the address width in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

I've been unable to use generics in VHDL and hence hdl_parameters in the TCL to paramterize address widths in SOPC 7.2. I'm afraid that I've found no alternative but to use fixed widths for component ports! Certainly in VHDL. e.g.

avs_control_address : in std_logic_vector(2 downto 0);

is OK but ..

avs_control_address : in std_logic_vector(addr_width-1 downto 0);

won't work and SOPC thinks the addr span is always 1 word!! i.e. (0 downto 0) regardless of the addr_width generic/parameter.

This is a real problem and I hope Altera get round to fixing this issue soon.