complex vector rotation implementation

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1. No exact pin location assignment for the pins.

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Open the pin assignment tool from Quartus menu bar and assign your design I/O signals to proper FPGA pins

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2. Synopsys Design Constaints File not found: 'lut.sdc', which is required by TimeQuest Timing Analyzer to get proper timing constrainsts.

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Create a lut.sdc file and add at least the minimal constraints. Read the TQ tutorial if you don't know how to.