Honored Contributor
Honored ContributorI am currently compiling for a10gx bsp. In the HTML reports the total BRAM count is 2531. In reality the total number of BRAM blocks are 2713. Below is the top.fit.summary
Fitter Status : Failed - Wed Jul 4 05:35:43 2018 Quartus Prime Version : 17.1.2 Build 304 01/31/2018 SJ Pro Edition Revision Name : top Top-level Entity Name : top Family : Arria 10 Device : 10AX115S2F45I1SG Timing Models : Final Logic utilization (in ALMs) : 357,354 / 427,200 ( 84 % ) Total registers : 558818 Total pins : 173 / 960 ( 18 % ) Total virtual pins : 0 Total block memory bits : 45,919,784 / 55,562,240 ( 83 % ) Total RAM Blocks : 2,669 / 2,713 ( 98 % ) Total DSP Blocks : 1,075 / 1,518 ( 71 % ) Total HSSI RX channels : 8 / 72 ( 11 % ) Total HSSI TX channels : 8 / 72 ( 11 % ) Total PLLs : 78 / 144 ( 54 % ) So RAM is just sufficient. Do you think I should still optimize the logic utilization? If so, when could I expect succesful compilation? (what percentage of logic utilization). Because the compilation failed again.
