compiling error with custom SOPC Builder component

I create a custom component using component editor directly. Because the custom component is just an interface to external device, so I can create it without any HDL source file.

Then component will generate *.tcl file automatically.

With the *.tcl file, SOPC Builder can instantiate the custom component into NiosII system.

Then I can generate the whole SOPC Builder system without any error.

In QuartusII, I instantiate the NiosII system in the top-level bdf file, then I try to compile it, but the following error occurs:

Error: Node instance "the_USB_AvalonInterface" instantiates undefined entity "USB_AvalonInterface"

I'm using QuartusII7.2 version.

After SOPC Builder system generation, it generate USB_AvalonInterface_inst.vhd automatically.

I look into USB_AvalonInterface_inst.vhd and can find that it try to instantiate USB_AvalonInterface which lead to the error showed above. Because component editor only create USB_AvalonInterface.tcl but not USB_AvalonInterface.vhd which should contain entity "USB_AvalonInterface".

How to resolve this problem? Is it a bug in 7.2?

As I remember, 7.1 can work in this case without any error.

I also find that only data ports are exported to the top interface of niosii system, the other ports such as rd/wr/cs/address arent exported.

The *.tcl file for the custom component generated by SOPC Builder automaticall showed below:

# TCL File Generated by Component Editor 7.2 on:
#  Wed Jan 16 16:49:09 CST 2008
#  DO NOT MODIFY
set_source_file ""
set_module "USB_AvalonInterface"
set_module_description "USB_AvalonInterface"
set_module_property "author" "CWG"
set_module_property "className" "USB_AvalonInterface"
set_module_property "displayName" "USB_AvalonInterface"
set_module_property "group" "FREQMeasure_AvalonInterface"
#  Module parameters
#  Interface clock
add_interface "clock" "clock" "sink" "asynchronous"
#  Ports in interface clock
add_port_to_interface "clock" "usb_clock" "clk"
set_port_direction_and_width "usb_clock" "input" "1"
#  Interface usb_slave
add_interface "usb_slave" "avalon_tristate" "slave" "clock"
set_interface_property "usb_slave" "isNonVolatileStorage" "false"
set_interface_property "usb_slave" "readLatency" "0"
set_interface_property "usb_slave" "holdTime" "0"
set_interface_property "usb_slave" "printableDevice" "false"
set_interface_property "usb_slave" "readWaitTime" "1"
set_interface_property "usb_slave" "setupTime" "0"
set_interface_property "usb_slave" "writeLatency" "0"
set_interface_property "usb_slave" "writeWaitTime" "0"
set_interface_property "usb_slave" "timingUnits" "Cycles"
set_interface_property "usb_slave" "minimumUninterruptedRunLength" "1"
set_interface_property "usb_slave" "activeCSThroughReadLatency" "false"
set_interface_property "usb_slave" "isMemoryDevice" "false"
set_interface_property "usb_slave" "maximumPendingReadTransactions" "0"
#  Ports in interface usb_slave
add_port_to_interface "usb_slave" "usb_address" "address"
set_port_direction_and_width "usb_address" "input" "8"
add_port_to_interface "usb_slave" "usb_cs_n" "chipselect_n"
set_port_direction_and_width "usb_cs_n" "input" "1"
add_port_to_interface "usb_slave" "usb_rd_n" "read_n"
set_port_direction_and_width "usb_rd_n" "input" "1"
add_port_to_interface "usb_slave" "usb_data" "data"
set_port_direction_and_width "usb_data" "bidir" "8"
add_port_to_interface "usb_slave" "usb_wr_n" "write_n"
set_port_direction_and_width "usb_wr_n" "input" "1"

I must mistake something , hope for help!