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Altera_Forum's avatar
Altera_Forum
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12 years ago

compiling a design that instantiate 4096 times the same module

Hi, I'm writing a vhdl top code that instantiates 4096 the same module (using vhdl generate statement). The module consists in a RAM, plus an adder and some other logic ... and 4096 of them sat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

yup, 6 hours about right.

I currently have a 80% full Stratix 4 that takes 4 hours on an i7, or 17 hours if I run DSE with 12 parrallel compiles (and It never meets timing) on the 6 core Xeon server.

Welcome to full FPGA compilations.