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Altera_Forum
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12 years ago

compiling a design that instantiate 4096 times the same module

Hi, I'm writing a vhdl top code that instantiates 4096 the same module (using vhdl generate statement). The module consists in a RAM, plus an adder and some other logic ... and 4096 of them sat...
Altera_Forum's avatar
Altera_Forum
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12 years ago

I don't know of any.

It looks like a hard problem anyway. Unlike an ASIC, where you can create a block and then simply replicate it exactly, in an FPGA each "identical" block has to be fitted to the FPGA logic and interconnect resources, making each one slightly different.

6 hour compile time sounds about right for a full big FPGA.