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Altera_Forum's avatar
Altera_Forum
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16 years ago

Compiler Options for EP1C20F400C7

Hi there,

i have a problem with the programming of a Nios Cyclone Dev. Kit with a EP1C20F400C7,

and i feel increasingly retarded for not being able to figure it out.

I have an old design compiled for this Dev. board which i can open and program,

however i can not compile the project and program the new sof file.

I tried Quartus II Web versions 5.1, 8.1 and 9 with the same results under Xp and Vista.

To fix the problem i am compiling a simple test program in verilog for the Ep1C20 with Clk and Reset inputs, the pin assignments seem to be in order (K5 for Clk, C4 for Reset), Quartus II informs me of no significant warnings.

Then i start the Programmer with the USB Blaster connected to the powered up and running Dev. Board, the device is correctly recognized via JTAG, the correct sof file is selected, Quartus informs me of successful configuration and programmer operation.

Only it's not successful.

At the end of the programming operation the error LED and the 8 segment LEDs flash for an instant, than the default configuration is loaded as indicated by blinking user LED.

I suspect the problem lies in some compiler configuration that i have overlooked, but so far i have been unable to come up with a solution. My old design with the working sof and pof files is from 2004, and i don't really remember there being any problems with project creation or compilation.

Has anyone any input on this? Every suggestion is appreciated,

Thanks in advance.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    This is my third attempt to post.. My previous posts don't seem to be taking, so if you get multiple answers, sorry.

    The most likely cause is the state of unused pins in your "Simple test program" in the earlier versions of quartus they default state of un-used pins, was tristated inputs with a pull-up, but at one point, they switch this to "outputs driving GND". Now if your board has a means for the FPGA to physically reset or power cycle the board base on the state of an FPGA pin, this can cause problems.

    This is changed under Assignments->Device->Device and Pin Assignments->Unused pins

    I Would recommend, either input tristated with weak pull-up or input tristated with bus-hold circuit.

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    This is my third attempt to post.. My previous posts don't seem to be taking, so if you get multiple answers, sorry.

    --- Quote End ---

    First of all thank you for replying so qickly, the whole situation of being stuck at this level in development was getting really frustrating,

    and second

    --- Quote Start ---

    "outputs driving GND"

    --- Quote End ---

    THANK YOU FOR THIS! YOU ARE AWESOME! That is it!

    I fiddled with the settings in the Device and Pin Assignments Dialog before,

    but i admit i didn't really know what i was doing, and since it worked with previous versions i didn't really expect there to be any significant changes. Shows what i know.

    Thanks again. :)
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    No Problem. Glad it helped. I ran into that issue before, so that's the only reason I knew what to try..

    Pete
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    This is changed under Assignments->Device->Device and Pin Assignments->Unused pins

    I Would recommend, either input tristated with weak pull-up or input tristated with bus-hold circuit.

    --- Quote End ---

    great advice