Honored Contributori have started with quartus 2, wrote a small module like the following in verilog but cannot compile,it takes to much time to compile (> 12 minutes) .... where is the problem?
module test(x1, x2, f); input x1,x2; output f; assign f = (x1 & ~x2) | (~x1 & x2); endmodule
Honored Contributori have the solution, quartus is installed on C/.... and my application was installed on a server. i have copied my application on C/ and now i can compile my module..
Honored ContributorThe code looks good (although I hate verilog and prefer SystemVerilog).
I advise you to test it. Your code would then look like this:
module test(
input x1,x2,
output f);
assign f = (x1 & ~x2) | (~x1 & x2);
endmodule
