Compilation Warning

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After I compile my project, I found out that under the Fitter section, I have all the 0 values except than Total pins. Also on the Timing Analyzer, i have a warning "No paths found for timing analysis"

Anyone knows what would have gone wrong? I need to have the details from the compilation report. Could it be some setting errors?

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Hi,

I would assume that your design is optimized away. Any warnings in your report files like

"No clock transition on..."? You can also look for open inputs (e.g. resets ...). Maybe you can post the messages from Analysis and Synthesis ?

Kind regards

GPK

Hi,

As Pletz said it appears that your design has been optimized away!

Very suspect lines in the report include

Warning (15610): No output dependent on input pin "clk"

Warning (15610): No output dependent on input pin "reset"

This basically means your top level reset and clock pins are not driving any logic!

Have you connected these pins on your top level correctly to the sub-modules?

Are you sure you haven't tied reset active somewhere in your top level?

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Hi,

As Pletz said it appears that your design has been optimized away!

Very suspect lines in the report include

Warning (15610): No output dependent on input pin "clk"

Warning (15610): No output dependent on input pin "reset"

This basically means your top level reset and clock pins are not driving any logic!

Have you connected these pins on your top level correctly to the sub-modules?

Are you sure you haven't tied reset active somewhere in your top level?

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hmm..what does it means as optimized way?

actually i only have one top level file. what does it means by tied reset active somewhere?

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hmm..what does it means as optimized way?

actually i only have one top level file. what does it means by tied reset active somewhere?

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Hi,

I have look to your report file. First thing I'm wondering about is the large number of duplicate registers. Duplicate register are merged with the default settings. I would recoomand to change this setting. Run a new compile and look into the RTL view, maybe you can see which inputs are not connected or why the synthesis tool recognized that the registers could be merged.

You can change the setting in following way:

Settings -> Analysis and Synthesis Setting -> More Settings -> Remove Duplicate Registers -> off

Kind regards

GPK

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hmm..what does it means as optimized way?

actually i only have one top level file. what does it means by tied reset active somewhere?

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It means that none of your input pins have any effect on any of of your output pins. (if you have any).

Therefore Quartus decides that the logic is redundant and removes it.

Regarding tying reset

An example might be that in your top level you have declared an input port called reset but that port is not actually connected to any internal logic. You might also have declared a signal in your top level called say reset_n and be using that within your processes. Just a guess really :confused:

I would just check that your input pins (clock and reset are really used within your processes)

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It means that none of your input pins have any effect on any of of your output pins. (if you have any).

Therefore Quartus decides that the logic is redundant and removes it.

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yupe. my output has no direct relation to the inputs.

so is this the main reason i dun get to have any logic elements values and no path for timing analysis in my compilation report?

Yes it is.

If the outputs are not dependent on the inputs then no logic will result!

How are you generating things like clock and reset etc if you are not using input pins?

If this is a test build then you might want to drive your outputs from the FSM outputs to ensure the FSM isn't optimized away!

Or you could use the "Preserve Fan-out Free Register Node" assignment on the signals you want to keep. (Maybe you plan to view them in SignalTap)

See the online help for more info on this assignment