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hmm..what does it means as optimized way?
actually i only have one top level file. what does it means by tied reset active somewhere?
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It means that none of your input pins have any effect on any of of your output pins. (if you have any).
Therefore Quartus decides that the logic is redundant and removes it.
Regarding tying reset
An example might be that in your top level you have declared an input port called reset but that port is not actually connected to any internal logic. You might also have declared a signal in your top level called say reset_n and be using that within your processes. Just a guess really :confused:
I would just check that your input pins (clock and reset are really used within your processes)
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