Honored Contributor
Honored ContributorGetting quite off-topic here...
I've been messing around with different kinds of location assignments, trying to release the fitter, but somehow it was always worse (what a wonder...). There is always a point where the skew ends up in a loop. We have some 20 clocks here, thereof about 5 asynchronous. The good part of the dividers are ripple counters (I hope there is no student or professor reading that now...). So somehow, I'm not really surprised by the bad result ;) The only disappointing thing is the clock gating conversion introduced in Q8.1. From a colleague I know that Synplify managed to convert the tree. Anyway, we are probably starting a new version this summer, so I'll try to fix this mess somewhat. They were running into problems on the ASIC as well, just much less. So back to the topic: This will also reduce the compilation time heavily I guess.
