Honored Contributor
Honored ContributorIf you have a gated clock, and therefore have clock skew so the latching clock is longer than the launching clock, you end up having to add delays to meet hold timing. So even though the requirement is 0ns, in essence it still has to add delay to meet timing. Naturally anything that can be done in the code to fix this would be good. (Like moving the gating signals from logic to drive the enable of the altclkctrl block...)
How long is the route time compared to placemen? Most designs it's much less, say 5%, but your design may be skewed. Also curious what the average and peak routing utilization is? (in .fit.rpt). And do you have Optimize Fast Corner checked? (I think you're aware of all this, just double-checking...)
