Compilation time for Quartus II 9.0

Are you saying that Q9.0 is optimize positive hold requirements inside the device and that's why it's taking longer? Note that when look at compile times, I always look at the fitter messages, as it breaks out placement time, physical synthesis time(which is part of total placement) and route time, just so I can monitor where the fitter is spending time, and when comparing different results, I know what changed.

If you have Assignments -> Fitter -> Optimize Hold Timing = All Paths, and Optimize Fast Corner checked, then you already have the cool settings to have the router add delays to meet your hold requirements. But naturally this increases routing resources and can make compile times get longer, or even make the design hard to route. This is expected in an FPGA with large clock skews.

(There is also an Assignment -> Analysys & Synthesis -> More Settings -> Auto Gated Clock Conversion, which could help a lot of it works on your design. I don't know enough about it, and there are plenty of gated clock implementations that can't be improved, but it's probably worth a try.)