Forum Discussion
Altera_Forum
Honored Contributor
16 years agoHi
I have a somewhat disappointing result for our design here: With Quartus 8.1, the fitter needs between 2h15 and 3h15 for different seeds, synthesis is 51min. With Quartus 9.0, the fitter needs between 3 and 6 hours, with the mean value around 5h. Synthesis is somewhat shorter (46min). I have to say that the design is made for an ASIC - and even there the clocking strategy is not very nice. For an FPGA it is disastrous. So if anyone has a cool trick with settings to remedy hold time violations due to clock skew - please tell me ;) I can't change the design for now... Thanks emanuel