Compilation process is funny in Quartus II

--- Quote Start ---

Hi everybody,

Currently I am working on a fancy Quartus II project in which compilation time takes more than 3h. I noticed than sometimes, if I completely perform the synthesis and fitting steps and then, for some irrelevant reason, I close the application (say because I had a meeting or it's the end of the day, whatever), when I reopen this project and try to perform the assembling processes to finally do some HW tests, everything starts from the beginning again. I mean, I see that the compilation project starts from the very first synthesis step, like if I had never completed this before (however I did). And what is more strange is that the project has not been changed since the last fitting; the only conflicting action here seems to be that I let Quartus rest for a while. Does anybody know any way to avoid this "phenomenon"? Perhaps there is an arcane trick (I pressume through command-line) to force the application to accept and work on the last synthesis and fitting results, as there is in some competitor's tools whose name starts with an 'X'. Thank you in advance!

Best regards,

P.

--- Quote End ---

Somewhere in the compiler settings you will find the option of "turn smart compilation on" and it "smartly" escapes initial stages but probably not fitting stage.

3 hours, more or less depends on the project size, fitting and timing closure, your PC etc so varies a lot and my personal experience is that xilinx ISE clutter of tools is slower than the compact quartus (plus now Timequest cluttered out) while SysGen is extremely slower than DSPBuilder (just to be fair).

--- Quote Start ---

Somewhere in the compiler settings you will find the option of "turn smart compilation on" and it "smartly" escapes initial stages but probably not fitting stage.

3 hours, more or less depends on the project size, fitting and timing closure, your PC etc so varies a lot and my personal experience is that xilinx ISE clutter of tools is slower than the compact quartus (plus now Timequest cluttered out) while SysGen is extremely slower than DSPBuilder (just to be fair).

--- Quote End ---

Kaz, thank you very much for your reply. The options you mention were already turned on, but they did not solve this little problem. I also tried to turn on the "Rapid recompile" feature, but no results either. It is like if Quartus II automatically discarded previous compilation results that were created before the beginning of the current session (i.e., before the starting time of the application). But this is just a conjecture, I have never put my nose on the very internal design of Q2.

Regarding the compilation time, let me say that my intention was not to complain about it, but only to highlight that this problem is a bit annoying (think about 3h of compilation at the end of the day, and three extra hours more the next morning just as a "punishment" for closing the application...). And the reference to the competitor's tools was more a reference to the option "force process up-to-date" that makes the Xilinx's ISE environment accept the last compilation results as valid and up-to date (though you have to manage it carefully, the results can be wrong if you made some changes on the design, obviously). Do you know a (command-line?) trick to achieve the same results in Quartus II? Or at least an alternative method to launch the assembler over the last fitting results without having to go back to the start if the application was closed.

Well, finally I don't want to enter into an argument about which design tools are the best; as you say, there are many variables that influence the compilation time and the productivity you get, including your pc's performance and your skills, but all that stuff is far way away from my question here. Anyway, I agree with you in one point: I firmly believe Timequest is lightyears ahead other timing analyzers.

Again, thank you for your reply.

I know tcl can allow a lot more control over Quartus but I am no fan of tcl.

http://www.altera.com/quartushelp/li...word=scripting

--- Quote Start ---

I know tcl can allow a lot more control over Quartus but I am no fan of tcl.

http://www.altera.com/quartushelp/li...word=scripting

--- Quote End ---

Uhmm, the link is broken, but I think I got what you are suggesting. It's a good idea, my intuition tells me that the quartus_asm application shouldn't mess with the date of the fitting results, but actually I've never tried it. Next time I have to close Quartus II after fitting some design but prior to the assembling process I will try to call the assembler through the TCL interpreter (if anybody is wondering how, check this out: http://www.altera.com/literature/hb/qts/qts_qii52002.pdf). If I ever succeed I will publish the solution in the forum. Thank you!

PD: I will appreciate any other suggestion, or any kind of TCL code snippet, of course.

--- Quote Start ---

Are you running the Assembler from the Task Manager on the left? I'm not a fan of that flow because it tries to be smart. (I'm guessing there's something besides just "resting" that makes it think it has to re-do everything, but I'm also guessing that it's making the wrong choice). If you go to Processing -> Start menu, all the individual commands can be run, and there are no "smarts" behind it. If you tell it to run the assembler, it runs the assembler. If you tell it to run EDA Tools, it runs those. Now, if you had never fit the design, the Assembler will give an error and say the fitter must be run, and it won't do it for you, but most likely in your case it will do just what you want.

--- Quote End ---

Rysc, you've just hit the jackpot, that solved the problem elegantly and without any TCL mess. Thank you!

Cheers,

P.