Compilation incompatibilities Modelsim-Quartus (component conditional generation)

Sorry, I didn't write the code myself and I'm very new to Altera and Altera's IP cores, so I was not really aware of that. But you are right.

We finally found a workaround that seems to work for both Quartus and Modelsim. If we DO declare the component ourselves but initialize these two ports:

clock1 : IN std_logic :='0';

clocken1 : IN std_logic :='0';

And then let them open in the instantiation:

clock1 => open,

clocken1 => open,

Modelsim does also compile it (no warnings or errors).

Probably not the best according to VHDL rules but it works for us.

Thank you for your support.

BR