Compilation incompatibilities Modelsim-Quartus (component conditional generation)

The altsyncram component is declared in the altera_mf library, so a local component is not required. This may be what your problem is, because the component declaration in the altera_mf_componts package has default values for the clocks and clocken if they are left unconnected (ie. left out of the port map, rather than left to open).

Modelsim is correct about the first instance, because "in" ports must be connected to something according to VHDL rules. Quartus is generally a bit more relaxed when it comes to language rules, but modelsim is not.

What you may need to do here is have two if... generates. one for Legacy and one for dual_clk, with a separate ram instantiation in each.

If you post thje full code, I may be able to have a look.