Altera_Forum
Honored Contributor
8 years agoCompilation Error
Hi i am getting the following error during compilation cu any one help me plz
Error (12005): Actual width (17) of port "read_address" on instance "KIKISMDWT:UVK|dual_ram:DUALRAM" is not compatible with the formal port width (5) declared by the instantiated entity COMPONENT dual_ram IS PORT ( clock1 : IN STD_LOGIC := '1'; clock2 : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (23 DOWNTO 0); read_address : IN STD_LOGIC_VECTOR (16 DOWNTO 0); write_address : IN STD_LOGIC_VECTOR (16 DOWNTO 0); wren : IN STD_LOGIC := '0'; q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) ); END COMPONENT; DUALRAM : dual_ram PORT MAP(clock1,clock2,data,read_address,write_address,wren,q);