Compilation error while compiling a variation of LPM_MUX in VHDL using precompiled libraries.

We are using quartus 19.1 to generate a variation of LPM_MUX in VHDL. We are using Cadence INCISIV 15.20.020 to compile this. Using the "Launch Simulation Library Compiler", we were able to generate VHDL compiled libraries. A cds.lib was also generated which maps the libraries.

The generated LPM_MUX variation in VHDL is as below.

cyclone_lpm_mux.vhd

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY lpm;

USE lpm.lpm_components.all;

ENTITY cyclone_lpm_mux IS

PORT

(

data0 : IN STD_LOGIC ;

data1 : IN STD_LOGIC ;

sel : IN STD_LOGIC ;

result : OUT STD_LOGIC

);

END cyclone_lpm_mux;

ARCHITECTURE SYN OF cyclone_lpm_mux IS

--type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);

SIGNAL sub_wire1 : STD_LOGIC ;

SIGNAL sub_wire2 : STD_LOGIC ;

SIGNAL sub_wire3 : STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0);

SIGNAL sub_wire4 : STD_LOGIC ;

SIGNAL sub_wire5 : STD_LOGIC ;

SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);

BEGIN

sub_wire4 <= data0;

sub_wire1 <= sub_wire0(0);

result <= sub_wire1;

sub_wire2 <= data1;

sub_wire3(1, 0) <= sub_wire2;

sub_wire3(0, 0) <= sub_wire4;

sub_wire5 <= sel;

sub_wire6(0) <= sub_wire5;

LPM_MUX_component : LPM_MUX

GENERIC MAP (

lpm_size => 2,

lpm_type => "LPM_MUX",

lpm_width => 1,

lpm_widths => 1

)

PORT MAP (

data => sub_wire3,

sel => sub_wire6,

result => sub_wire0

);

END SYN;

No when we try compiling using the irun command

irun -compile -cdslib cds.lib -v93 cyclone_lpm_mux.vhd,

we get the error

USE lpm.lpm_components.all;

|

ncvhdl_p: *E,SELLIB (cyclone_lpm_mux.vhd,42|7): unit (LPM_COMPONENTS) not found in library (LPM).

I did a grep on the compiled library generated by the quartus for lpm_components. It is not present there.

Can anyone let us know what is wrong.