Forum Discussion
Honored ContributorComparison between old value and new value
Hi All,
Its a very simple question but I am unable to do that. Below is my code. I want to store signal data_o_new to signal data_o_old and then compare these signals with each other and do increment or decrement until these two signals become same. data_o_new is coming from an ip. Please help me... thanks Architechture starts here: Begin data_o_old <= data_o_new; data_o <= data_o_old; fading: PROCESS(clk) Begin if rising_edge(clk) then if data_o_new > data_o_old then data_o_old <= data_o_old + 1; elsif data_o_new < data_o_old then data_o_old <= data_o_old - 1; else data_o_old <= data_o_new; end if; end if; end process; end Architecture;15 Replies
Altera_Forumhm... have you seen generated RTL? it seems you need one or two more registers. does new value arrive every clock-cycle ?
is it just wire in synthesisdata_o_old <= data_o_new; data_o <= data_o_old;- Altera_Forum
What exactly is the problem you are having?
- Altera_Forum
My problem is that I dont understand how do I manage to store new value to old value signal... then that stored value, I need to decrement or increment it according to new value. After incrementing or decrementing, it should stop when old value will be equal to new value. Hope you understand it. If no, then dont hesitate to ask again. thanks
- Altera_Forum
Hi Alex96,
I don't see RTL yet. And new value is not coming every clock. it changes when my temperature changes. but don't worry about temperature. Acutally, my ip is generating new value then I need to store it to a signal and decrement or increment it until it becomes equal to the new value. - Altera_Forum
oh hope you will remove some lsb from comparison and pay attention to place one more register. So do you want to do work like SAR ADC ???
- Altera_Forum
You still havent explained youself - your current code appears to do what you want - so I dont see the problem? It load in a new value when new and old are the same.
- Altera_Forum
I am a little bit confused, maybe my VHDL coding is not that good.
You did wire assignment as Alex pointed out. Doesn't that make your old value directly taking the new value? Why do you need the process to add/subtract the old value? Also the else statement in your process is weird, which directly take in the new value when it is not more or less then new value. I think maybe you need to do something like this: Architechture starts here: Begin -- not needed -- data_o_old <= data_o_new; -- assuming that you have data_o as an output data_o <= data_o_old; fading: PROCESS(clk) Begin if rising_edge(clk) then if data_o_new > data_o_old then data_o_old <= data_o_old + 1; elsif data_o_new < data_o_old then data_o_old <= data_o_old - 1; else data_o_old <= data_o_old; -- latch the old value if not more or less new data end if; end if; end process; end Architecture; Also I assume that the new data does not change every cycle. - Altera_Forum
Hi mikedsouze,
thanks for the reply... your idea is good about latching but you didn't assign new value to old value anywhere. This assignment is necessary because I need to take the new value and hold it into a signal until new value changes. And yes new value is not changing at every cycle but it is coming on every cycle with constant value. - Altera_Forum
Sorry Alex, I described you wrong yesterday. the new value is coming on every cycle having constant value. And I don't understand you SAR ADC technique. Can you please explain. thanks
- Altera_Forum
Hi Tricky,
Let me explain by an example. -- let say new_value is incrementing or decrementing after 1 msec -- means new_value is constant for every 1 msec -- let say new_value = 4095 for 1 msec then new_value = 3998 for 1 msec then new_value = 3886 (decimal values) and so on... Now I want to make smooth transition between 4095 to 3998 and 3998 to 3886. I dont want abrupt change of new value. that's why I store the new value to a signal then do increment or decrement to that signal while my signal is going to output having a smooth transition.
