Comparison between old value and new value

I am a little bit confused, maybe my VHDL coding is not that good.

You did wire assignment as Alex pointed out. Doesn't that make your old value directly taking the new value? Why do you need the process to add/subtract the old value?

Also the else statement in your process is weird, which directly take in the new value when it is not more or less then new value. I think maybe you need to do something like this:

Architechture starts here:

Begin

-- not needed

-- data_o_old <= data_o_new;

-- assuming that you have data_o as an output

data_o <= data_o_old;

fading: PROCESS(clk)

Begin

if rising_edge(clk) then

if data_o_new > data_o_old then

data_o_old <= data_o_old + 1;

elsif data_o_new < data_o_old then

data_o_old <= data_o_old - 1;

else

data_o_old <= data_o_old; -- latch the old value if not more or less new data

end if;

end if;

end process;

end Architecture;

Also I assume that the new data does not change every cycle.