Forum Discussion
Altera_Forum
Honored Contributor
10 years agothen why not do something like this?
signal value_ref : unsigned(Nbits-1 downto 0);
signal output_ref : unsigned(Nbits-1 downto 0);
process(clk)
begin
if rising_edge(clk) then
value_ref <= new_value;
if value_ref > output_ref then
output_ref <= output_ref +1;
elsif value_ref < output_ref then
output_ref <= output_ref -1;
end if;
end if;
end process;
op <= output_ref;
Here, the output never changes dramatically, but is gradually pulled towards your new value.