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You possibly have a multiple bit asynchronous load under the reset condition?
Generally, I can't say if Quartus is always showing the code generating the latch, but it mostly works for me.
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Here is what I have for the reset block:
Accu_Phi_in <= 12'b000001010111;
Accu_Phi_inm <= 12'b111110101001;
L <= 3'b000;
Iplus <= {Iplusin[WIDTH-1],Iplusin[WIDTH-1:0]};
Qplus <= {Qplusin[WIDTH-1],Qplusin[WIDTH-1:0]};
Iminus <= {Iminusin[WIDTH-1],Iminusin[WIDTH-1:0]};
Qminus <= {Qminusin[WIDTH-1],Qminusin[WIDTH-1:0]};
All the variables on the left are register variables, and on the right are inputs to this submodule or some constants. This is for the initialization for the calculation of a new group of input data. The timing is controlled by the clocks (reset, clk). Is this something related to "multiple bit asynchronous load"?
Besides, one warning for each bit for the four variables (Iplus, Qplus, Iminus, Qminus) --- 52 warnings, which says each bit is converted into an equivalent circuit using its corresponding register.
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