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Altera_Forum's avatar
Altera_Forum
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12 years ago

combinational loops as latches

I got a warning: TimeQuest Timing Analyzer is analyzing 24 combinational loops as latches. I was told this was caused by incomplete output changes corresponding to the input changes. That is, some in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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Unlikely, it shows all latch instances in your design below the warning, if you unfold it.

Not all latches can be avoided, some are introduced by Quartus, e.g. the previously discussed "equivalent circuit" for asynchronously loaded registers.

--- Quote End ---

I got about 40 sub-warnings for this "equivalent circuit " problem when I unfold this "equivalent circuit " warning.

What if I simply ignore this "combinational loops as latches" problem? I know this could affect the timing analysis, but what could be the worst situation that would happen?