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Altera_Forum
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12 years ago

combinational loops as latches produced while using generate & for

PLease see the attached files. I am trying to get some feelings on warnings for combinational loops as latches. The first attached file generates many inferred latches. By adding a clocks, the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

It's completely unclear what you are trying to achieve. You are describing asynchronous "memory" by writing data under always @(*). It can be only synthesized as combinational loop with recent Altera FPGA.

There's no significant difference between both examples regarding latch inference.