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Altera_Forum's avatar
Altera_Forum
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15 years ago

Combinational loop

When I start up Timing Analyzer GUI (quartus_staw) and read my sdc file I then try one of the reports (report clocks). I get a message saying "Critical Warning: Design contains combinational loop of...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Either way, how do I convert a node name to a port name so that I can either set_disable_timing or set_false_path?

This is just a simple tool question. How do I break a combinational loop so that I can make progress? Leave the long term solution up to me. For now, all I want to know is how to take the information the tool is spitting out (node name) and convert it to something I can use (port name) to break the combinational loop.

Once I have that I can actually use the tool to analyze what the real problem is. Right now the tool is dead in the water trying to estimate timing F-O-R-E-V-E-R.