Honored Contributor
Honored ContributorMy advice and keep in mind I ditched VHDL long ago for schematic design against my choice (but I'm never going back now that I know verilog....)
- Split register operations from combination logic - Make sure all synchronous (register) operations are on a clock edge to avoid latches which are bad news in a FPGA - In your case use 2D indexing since you are working with groups of signals at a time. There is no need to come up with a bunch of signal names for different conditions when the condition itself can select the functionality *. All three of those points can be made of VHDL and verilog (and schematics in some ways) so as far as I'm concerned all three are good design practice. The first point I make I want to stress since I run into many so called "experienced designers" who don't follow that rule which makes their code a mysterious "who knows what comes out of the synthesis engine" mess...... * Note: This isn't always true when optimizing so take with a grain of salt.
