Code not working for Quartus 2

Without looking at your code, I wonder if you included the file for the mem package at "Project --> Add/Remove Files in Project" and listed it before the file for FA_calc.

If that's not the problem, you should show your error message here.

I did same stuff but still Error..

Error (10633): VHDL Case Statement or If Statement error at FA_calc.vhd(62): can't synthesize condition that contains an isolated 'EVENT predefined attribute.

Error: Can't elaborate top-level user hierarchy

Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 10 warnings

Info: Allocated 143 megabytes of memory during processing

Error: Processing ended: Tue Jul 31 09:35:43 2007

Error: Elapsed time: 00:00:02

Error: Quartus II Full Compilation was unsuccessful. 2 errors, 10 warnings

Please, Help me out.

Is there any other way (tool) to transfer my code in FPGA ??

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Is there any other way (tool) to transfer my code in FPGA ??

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I don't think it would help with this error, but you can use any synthesis tool that is compatible with Quartus. Quartus particularly supports the third-party tools listed at "Assignments --> EDA Tool Settings --> Design Entry/Synthesis --> Tool name".

When you get an error or warning that you don't understand, right click the message and select "Help". The help isn't always helpful, but in this case it tells you what you need to know.

Also right click the error and select "Locate --> Locate in Design File". (This menu option is in bold text, which means you can activate it by double clicking the message instead of right clicking.) The error locates to:

if load'event then ---- depend on the switch

The help page, copied below, is saying that synthesis considers "load" to be a clock signal because of the 'event, but you didn't specify whether to clock on the rising edge or the falling edge. The FPGA registers require you to use just one clock edge.

If you intended to do an asynchronous load, then you need to code it differently. In the Quartus handbook, see Volume 1, Section II, Chapter 6. Asynchronous load is illustrated in "Example 6–31. VHDL D-Type Flipflop (Register) with ena, aclr and aload Control Signals". An asynchronous load requires that the registers still have some clock.

If you intended to use a latch without a clock, then there is an acceptable way to code that, but clocked registers should be used instead of latches whenever possible.

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VHDL Case Statement or If Statement error at <location>: can't synthesize condition that contains an isolated 'EVENT predefined attribute

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CAUSE: In a Case Statement or If Statement at the specified location in a VHDL Design File (.vhd), you used an isolated 'EVENT predefined attribute on a variable or signal, that is, you did not combine the predefined attribute with another, level-test condition to form an explicit clock edge. Quartus II Integrated Synthesis cannot synthesize conditions based on isolated 'EVENT predefined attributes. For example, in the following code, an If Statement uses an isolated 'EVENT predefined attribute to test for an event on the signal clk:

my_dff : PROCESS (clk, rst)BEGIN IF rst = '1' THEN q <= '0'; ELSIF clk'EVENT THEN q <= data; END IF;END PROCESS;

The Process Statement containing the If Statement may be attempting to create a register that is sensitive to both the positive and negative edges of clk. However, Quartus II Integrated Synthesis cannot generate logic to implement a dual-edge register in a device.

ACTION: Modify the Case or If Statement so that it represents a valid clock edge, or remove the isolated 'EVENT predefined attribute. For the previous example, you can rewrite the If Statement so that it infers a positive edge-triggered register:

my_dff : PROCESS (clk, rst)BEGIN IF rst = '1' THEN q <= '0'; ELSIF clk'EVENT and clk = '1' THEN q <= data; END IF;END PROCESS;

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Thanks for your help..

i have made small chage in my code but here i could not able to assign value..ie..

code :-

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

use work.mem.all;

entity FA_calc is

port( clk : std_logic;

MTmux : in std_logic_vector(width-2 downto 0);

MTdat : in std_logic_vector(width-2 downto 0);

MTout : out word2;

MTout_analyzer : out std_logic_vector(width-2 downto 0);

load : in std_logic

);

end FA_calc;

architecture behav of FA_calc is

signal sig_mem : word1;

signal sig_out : word3;

--signal cnt1: integer range 0 to 7 ;

--signal counter : std_logic_vector(12 downto 0) := "0000000000000";

--variable cnt : integer range 0 to 6720;

signal clkenable,num : std_logic;

signal wire1: std_logic;

begin

clkdiv : process(clk,MTmux)

variable cnt: integer range 0 to 2 ;

variable cnt1: integer range 0 to 7 ;

begin

clkenable <= '1';

if clk = '1' and clk'event then

--counter <= counter + 1;

cnt := cnt + 1;

if (cnt = 2) then

cnt1 := cnt1 +1;

case MTmux is

when "000" =>

sig_mem(0)(width-1 downto 1) <= MTdat;

when "001" =>

sig_mem(1)(width-1 downto 1) <= MTdat;

when "010" =>

sig_mem(2)(width-1 downto 1) <= MTdat;

when "011" =>

sig_mem(3)(width-1 downto 1) <= MTdat;

when "100" =>

sig_mem(4)(width-1 downto 1) <= MTdat;

when "101" =>

sig_mem(5)(width-1 downto 1) <= MTdat;

when "110" =>

sig_mem(6)(width-1 downto 1) <= MTdat;

when others =>

NULL;

end case;

cnt := 0;

if (cnt1 =4) then

sig_mem(1)(0) <= load;

clkenable <= '0';

end if;

end if;

end if;

end process;

ld : process(load,clkenable,sig_mem)

begin

if clkenable ='0' then

-- sig_mem(1)(0) <= '0';

sig_mem(1)(0) <= load;

for i in 0 to 5 loop

case sig_mem(i+1) is

when "0000" =>

sig_out(i+1)(width-2 downto 0) <= "000";

when "0100" =>

sig_out(i+1)(width-2 downto 0) <= "000";

when "1100" =>

sig_out(i+1)(width-2 downto 0) <= "001";

when "1110" =>

sig_out(i+1)(width-2 downto 0) <= "001";

wire1 <= '0';

when "0110" =>

sig_out(i+1)(width-2 downto 0) <= "011";

when "0010" =>

sig_out(i+1)(width-2 downto 0) <= "011";

when "1010" =>

sig_out(i+1)(width-2 downto 0) <= "010";

when "1011" =>

sig_out(i+1)(width-2 downto 0) <= "010";

when "0011" =>

sig_out(i+1)(width-2 downto 0) <= "110";

when "0111" =>

sig_out(i+1)(width-2 downto 0) <= "110";

when "1111" =>

sig_out(i+1)(width-2 downto 0) <= "111";

when "1101" =>

sig_out(i+1)(width-2 downto 0) <= "111";

when "0101" =>

sig_out(i+1)(width-2 downto 0) <= "101";

when "0001" =>

sig_out(i+1)(width-2 downto 0) <= "101";

when "1001" =>

sig_out(i+1)(width-2 downto 0) <= "100";

when "1000" =>

sig_out(i+1)(width-2 downto 0) <= "100";

when others =>

NULL;

end case;

sig_mem(i+2)(0) <= sig_out(i+1)(width-2)

end loop;

end if;

end process ld;

-- ld1 : process(sig_mem)

-- begin

-- sig_mem(2)(0) <= sig_out(2);

-- end process ld1;

end behav;

sig_mem(i+2)(0) <= sig_out(i+1)(width-2) :- here out put of first loop is the input of the Sig_mem but i could not able to assign my value..Any idea how to assign last output of2nd bit is the input of the next sig_mem o bit ??

Thanks a lot.