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Altera_Forum
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18 years agoI did same stuff but still Error..
Error (10633): VHDL Case Statement or If Statement error at FA_calc.vhd(62): can't synthesize condition that contains an isolated 'EVENT predefined attribute. Error: Can't elaborate top-level user hierarchy Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 10 warnings Info: Allocated 143 megabytes of memory during processing Error: Processing ended: Tue Jul 31 09:35:43 2007 Error: Elapsed time: 00:00:02 Error: Quartus II Full Compilation was unsuccessful. 2 errors, 10 warnings Please, Help me out. Is there any other way (tool) to transfer my code in FPGA ??