Code not working for Quartus 2

Thanks for your help..

i have made small chage in my code but here i could not able to assign value..ie..

code :-

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

use work.mem.all;

entity FA_calc is

port( clk : std_logic;

MTmux : in std_logic_vector(width-2 downto 0);

MTdat : in std_logic_vector(width-2 downto 0);

MTout : out word2;

MTout_analyzer : out std_logic_vector(width-2 downto 0);

load : in std_logic

);

end FA_calc;

architecture behav of FA_calc is

signal sig_mem : word1;

signal sig_out : word3;

--signal cnt1: integer range 0 to 7 ;

--signal counter : std_logic_vector(12 downto 0) := "0000000000000";

--variable cnt : integer range 0 to 6720;

signal clkenable,num : std_logic;

signal wire1: std_logic;

begin

clkdiv : process(clk,MTmux)

variable cnt: integer range 0 to 2 ;

variable cnt1: integer range 0 to 7 ;

begin

clkenable <= '1';

if clk = '1' and clk'event then

--counter <= counter + 1;

cnt := cnt + 1;

if (cnt = 2) then

cnt1 := cnt1 +1;

case MTmux is

when "000" =>

sig_mem(0)(width-1 downto 1) <= MTdat;

when "001" =>

sig_mem(1)(width-1 downto 1) <= MTdat;

when "010" =>

sig_mem(2)(width-1 downto 1) <= MTdat;

when "011" =>

sig_mem(3)(width-1 downto 1) <= MTdat;

when "100" =>

sig_mem(4)(width-1 downto 1) <= MTdat;

when "101" =>

sig_mem(5)(width-1 downto 1) <= MTdat;

when "110" =>

sig_mem(6)(width-1 downto 1) <= MTdat;

when others =>

NULL;

end case;

cnt := 0;

if (cnt1 =4) then

sig_mem(1)(0) <= load;

clkenable <= '0';

end if;

end if;

end if;

end process;

ld : process(load,clkenable,sig_mem)

begin

if clkenable ='0' then

-- sig_mem(1)(0) <= '0';

sig_mem(1)(0) <= load;

for i in 0 to 5 loop

case sig_mem(i+1) is

when "0000" =>

sig_out(i+1)(width-2 downto 0) <= "000";

when "0100" =>

sig_out(i+1)(width-2 downto 0) <= "000";

when "1100" =>

sig_out(i+1)(width-2 downto 0) <= "001";

when "1110" =>

sig_out(i+1)(width-2 downto 0) <= "001";

wire1 <= '0';

when "0110" =>

sig_out(i+1)(width-2 downto 0) <= "011";

when "0010" =>

sig_out(i+1)(width-2 downto 0) <= "011";

when "1010" =>

sig_out(i+1)(width-2 downto 0) <= "010";

when "1011" =>

sig_out(i+1)(width-2 downto 0) <= "010";

when "0011" =>

sig_out(i+1)(width-2 downto 0) <= "110";

when "0111" =>

sig_out(i+1)(width-2 downto 0) <= "110";

when "1111" =>

sig_out(i+1)(width-2 downto 0) <= "111";

when "1101" =>

sig_out(i+1)(width-2 downto 0) <= "111";

when "0101" =>

sig_out(i+1)(width-2 downto 0) <= "101";

when "0001" =>

sig_out(i+1)(width-2 downto 0) <= "101";

when "1001" =>

sig_out(i+1)(width-2 downto 0) <= "100";

when "1000" =>

sig_out(i+1)(width-2 downto 0) <= "100";

when others =>

NULL;

end case;

sig_mem(i+2)(0) <= sig_out(i+1)(width-2)

end loop;

end if;

end process ld;

-- ld1 : process(sig_mem)

-- begin

-- sig_mem(2)(0) <= sig_out(2);

-- end process ld1;

end behav;

sig_mem(i+2)(0) <= sig_out(i+1)(width-2) :- here out put of first loop is the input of the Sig_mem but i could not able to assign my value..Any idea how to assign last output of2nd bit is the input of the next sig_mem o bit ??

Thanks a lot.