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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Code from "MIT press.." Problem

Code:

----- Solution 1: in/out=SIGNED ----------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

------------------------------------------

ENTITY adder1 ISPORT ( a, b : IN SIGNED (3 DOWNTO 0);

sum : OUT SIGNED (4 DOWNTO 0));

END adder1;

------------------------------------------

ARCHITECTURE adder1 OF adder1 IS

BEGIN

sum <= a + b;

END adder1;

and quartus give a erro: sum have 5 element but a and b only have 4 element.

help me, i need use operator "+".

sorry for my english

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    first, I think you need to add a "use ieee.numeric_std.all;" to be able to use the unsigned and signed types.

    Then the + operator only works on vectors with the same length. You should convert a and b to 5-bit vectors before adding them. Something like: 

    sum <= resize(a,5) + resize(b,5);

    The resize function works with both unsigned and signed vectors.