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Altera_Forum
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11 years ago

Code for a pushbutton to produce an enable signal for a time delay generator

hi all i’m trying to realize a very small Project, for further and more complex projects . I wrote a synthesizable code to accomplish this – when i hit a pushbutton fpga should light a led and s...
Altera_Forum's avatar
Altera_Forum
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11 years ago

HDL is supposed to describe the behaviour of a system which will be eventually synthesized into actual logic gates.

Consider what you are requesting to the synthesis tool with the following lines you wrote:

if falling_edge (buton) then

deljenen <='1'; else

deljenen <='0';

So, deljenen is high only when buton presents a falling edge. In all other cases is low !

Then, how long does deljenen pulse last?!? How can you implement this with flip-flops and/or logic gates?

The correct way of operation is using clk to sample buton signal into a register and use it to detect the falling edge.