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Altera_Forum's avatar
Altera_Forum
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11 years ago

Code compiling errore

Hellow every bidy;

I faced an errore during compilation of my code on modelsim. the errore displayed " cannot index the result of a type conversion. ". and the errore apears in this line

if std_logic_vector(conv_unsigned(ref, 3))(2) = '0' then

How can I solve this problem?

Thanks.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    What is the name of the signal you are trying to index into? Surely it is not "std_logic_vector".

    Replace "std_logic_vector" with the signal name you are trying to compare to '0'.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Thanks for ur attension Mr ghogerheiden

    I replaced the std_logic_vector ststement and the rrrore removed

    but now i faced another errore wich is "bSigned <= conv_signed(-conv_integer(b), SIG_WIDTH));"

    in this line

    bSigned <= conv_signed(-conv_integer(b), SIG_WIDTH));

    can u help me
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    If you could post more of the code (for instance where you declare bSigned) and the actual error you are seeing it would be helpful.

    At a glance though, I'm not sure you can include the minus sign in the statement bSigned <= conv_signed(-conv_integer(b), SIG_WIDTH));

    That could be the problem. You may want to convert it to signed first then negate it?

    More information would help.