Code Check - Traffic Simulation

Testbench code apparently was not needed.

I did receive warnings but to me it read as though it was populating the sensitivity list with the inputs and outputs listed within the code.

In then end I just decided to scrap the whole thing and start from scratch, end result was pretty close to what was required.

Thank you for the input though, I have only done VHDL for about 2 weeks now and electronics is hardly my forte, more of a maths and programming man myself.

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My question is: where is the testbench code?

Second question: why have you put clock in the state machine sensitivity list, when it is clearly not a clocked process? and the comment is worrying, because it shows lack of understanding of VHDL:

process (clock) begin -- only list clock, program auto fills required variables

Quartus wont do any auto-filling for you. It will throw warnings about missing signals (note - not variables), but it ignores sensitivity lists, so you wont see a "problem". If you had a testbench, you would see that you would get many problems.

thurdly - you state machine proces produces latches - these are not recommended. You need to assign all signals in ALL cases in an asynchronous process (it is not synchronous, it is asynchronous, despite your comments).

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