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Altera_Forum's avatar
Altera_Forum
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12 years ago

close loop at Test Bench

Hi ,

i want to close loop back at the Test bench between the transmitted data from transmitter to the receiver .

both transmitter and receiver implemented at VHDL and they are known to the top .

a,b - output ports

c,d - input ports

i instantiate the output from transmitter entity - serial_out is the output of the generator entity inside transmitter entity :

serial_out => a ;

i instantiate the output from top entity :

a => b ;

i instantiate the output b to input of the top from test bench to close the loop :

b => c ;

i instantiate the input from top entity :

c => d ;

i instantiate the input from receiver entity - serial_in is the input of the receiver sub entity inside receiver entity:

d=> ser_in ;

after simulation at modelsim there are error massage :

" Unknown formal identifier " for a,b,c,d .

what did i do wrong ?

do i need to instantiate the program deferentially ?

file attached .

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  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    At the Rx file ser_in as input port ,

    At the Rx file i declare data_in as signal and connect : Data_in=> Data_in_D .

    There are 11 errors at Rx file after compiling .

    one of the errors is :

    1. ** Error: D:/Final Project/Technical/Top/hdl/Rx.vhd(34): (vcom-1136) Unknown identifier "Data_in_D".

    Data_in_D is the input port to MetaFix - declared at Rx file . i tried to declare it as a signal at Rx file but still it has the same error .

    --- Quote End ---

    No it is not declared in rx_vhd. It is port to submodule(Metfix). Thus it is unknown at rx_vhd.

    Just make a search for every errored signal and see if it is declared.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi kaz ,

    i'm a little confused ... i did defined data_in , data_in_D and all the rest of the signals as signals at Rx.vhd and still there are many errors .

    lines 17-26 at Rx.vhd :

    signal data_in : std_logic;

    signal Data_in_D : std_logic;

    signal PN_in : std_logic; -- PN_in is the output of the block PN_Transmitter

    signal cmp_out : std_logic; -- cmp_out is the output of the block comparator

    signal reg_in :std_logic;

    signal reg_in_signal1: std_logic;

    signal cmp_in_signal1: std_logic_vector(7 downto 0);

    signal cmp_in_signal2: std_logic_vector(7 downto 0);

    signal x : std_logic; -- x is the comparator output

    signal PN_out2 : std_logic; -- PN_out2 is the second PRBS output

    what do i need to do more ?
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    The error relates to the metafix entity. It has no port called data_in, its called data_in_d.

    And I suspect the rest of the problems are similar (you named the ports incorrectly, not the signals.

    On another note - some of these connections do nothing. For example, in RX, the data_in_d signal is connected to nothing.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    i changes the instanstiation order and now it compile without errors .

    Thanks a lot guys , you're awesome !