close loop at Test Bench

Hi kaz ,

i'm a little confused ... i did defined data_in , data_in_D and all the rest of the signals as signals at Rx.vhd and still there are many errors .

lines 17-26 at Rx.vhd :

signal data_in : std_logic;

signal Data_in_D : std_logic;

signal PN_in : std_logic; -- PN_in is the output of the block PN_Transmitter

signal cmp_out : std_logic; -- cmp_out is the output of the block comparator

signal reg_in :std_logic;

signal reg_in_signal1: std_logic;

signal cmp_in_signal1: std_logic_vector(7 downto 0);

signal cmp_in_signal2: std_logic_vector(7 downto 0);

signal x : std_logic; -- x is the comparator output

signal PN_out2 : std_logic; -- PN_out2 is the second PRBS output

what do i need to do more ?